interface dsp_cac_bus();
    logic   [0:0]  WR_REQ_CAC;
    logic   [0:0]  WR_VLD_CAC;
    logic   [17:0] WR_ADDR_CAC;
    logic   [0:0]  WR_DATA_VLD_CAC;
    logic   [29:0] WR_DATA_VALUE_CAC;
    
    logic   [0:0]  RD_DATA_VLD_CAC;
    logic   [29:0] RD_DATA_VALUE_CAC;

    
    logic   [5:0]  CAC_SRAM; //retain or discard?  must retained for calculating wr_addr
    logic   [0:0]  CAC_SHARE;
    
    modport dsp_ports(
    output RD_DATA_VLD_CAC,
    output RD_DATA_VALUE_CAC,
    output WR_REQ_CAC,
    output WR_DATA_VLD_CAC,
    output WR_DATA_VALUE_CAC,
    output CAC_SRAM,
    output CAC_SHARE,
    input  WR_VLD_CAC,
    input  WR_ADDR_CAC
    );

    modport cac_ports(
    input   RD_DATA_VLD_CAC,
    input   RD_DATA_VALUE_CAC,


    input   WR_DATA_VLD_CAC,
    input   WR_DATA_VALUE_CAC,

    input   CAC_SRAM,
    input   CAC_SHARE,
    input   WR_REQ_CAC,
    output  WR_VLD_CAC,
    output  WR_ADDR_CAC
    );

endinterface
